Also in the Information tab you can also set the top-level simulation model name and Destination directory. Go back to the Information page and see that the build specification name has changed to “FPGA Add Test” to match the name of your VI.
#Ni icycle simulator#
For this example leave these as the default value.įigure 7. In the Source Files Tab Select the VI to Simulate and the Signals to Expose in the Simulator
On this tab you can specify different signals that will be automatically added to the simulation waveform. In the dialog box that appears, set the top-level VI to simulate by navigating to the Source Files tab and selecting FPGA Add Test.vi. To create the build specification, right-click Build Specifications under FPGA Target and select New»Simulation Export.įigure 6. Create a Simulation Export Build Specification Create a simulation export build specification under FPGA Target.Next you will generate the simulation export files, including the VHDL test bench, which you will modify and then use to execute a simulation in ISim. Right-click on the PXI-7854R target in the Project Explorer window and select Execute VI On»Third-Party Simulator.įigure 5. Select the Third-Party Simulator Execution Mode for the FPGA Target To configure the execution mode of the FPGA target.In LabVIEW, select Tools»Options to display the Options dialog box, then select FPGA Module from the Category list.įrom the Simulator pull-down menu, select ISim.įigure 4. Configure LabVIEW to Export Simulation Files to ISim.Note: The completed VI is available in the attached lv_fpga_isim_ex files.įigure 3. Create a VI to benchmark the execution of the Add function in different loop typesĬonfigure the LabVIEW FPGA Module for Simulationīefore you build a simulation export, you need to configure LabVIEW to export to ISim. Since the simulation also accounts for communication delays between the LabVIEW host interface and the FPGA, the start delay also ensures that in the simulation the written data has been loaded on the registers before the Add functions are allowed to execute. A sequence structure encapsulates the loops in order to control when the loop execution starts, and the start Boolean triggers the test.
This VI benchmarks the execution time difference between using an Add function in a normal while loop versus a single-cycle timed loop (SCTL).Īs show in Figure 3 below, each loop contains an Add function and an indicator.Refer to the target hardware documentation for information about simulation support.Īdd a new VI under the PXI-7854R target and name the VI FPGA Add Test.vi.įigure 2. Add the FPGA target and a New VI Note: Support for cycle-accurate simulation varies by FPGA target.
#Ni icycle series#
For this example, use an NI PXI-7854R R Series Multifunction RIO device. The target should support LabVIEW FPGA simulation. Note: If you use the attached lv_fpga_isim_ex project files, you can skip this section.Ĭreate a LabVIEW project and save the project as LV FPGA ISim Example.lvproj. The simulation example will compare an Add function executing in a normal versus a single-cycle timed loop in a LabVIEW FPGA VI.įirst, create a new LabVIEW FPGA project and an FPGA VI to test in ISim.
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